AI Development Company in Austin

Semiconductor Design

An Austin-based semiconductor company designing custom processors for edge AI applications (automotive, industrial IoT, consumer electronics) faced an exponential design space problem. Each processor design involved 340+ configurable parameters (cache sizes, pipeline depth, execution unit configurations, memory hierarchy, interconnect topology, power management modes). Full simulation of a single design configuration took 4-6 hours on their EDA cluster (Synopsys VCS for functional simulation, PrimeTime for timing analysis). Evaluating the full design space — even a representative sample — was computationally impossible: 340 parameters with multiple options each created a space of 10^80+ configurations (more than atoms in the observable universe). The design team of 22 engineers used experience-guided manual exploration, evaluating approximately 800 design points per tape-out cycle (6 months). They consistently worried that better configurations existed in the unexplored design space. For their latest processor (targeting autonomous driving inference at 15 TOPS within a 5W power envelope), the performance-power-area trade-off was critical: missing the target meant losing the automotive OEM design win (a $120 million annual revenue opportunity over 5 years). Previous tape-outs had achieved 85-90% of theoretical optimal performance — the design team believed 5-10% performance improvement was possible but couldn't find it through manual exploration.

We built a multi-fidelity design space exploration system combining ML surrogate models with physics-informed constraints. (1) Training data pipeline: automated extraction from 5 years of simulation results (18,000 design point evaluations across previous projects). Each data point included: the 340 design parameters, functional simulation results (performance, throughput, latency), timing analysis results (critical path delay, clock frequency achievable), power analysis results (dynamic power, leakage power, total thermal design power), and area estimates (die size, which directly impacts manufacturing cost). We normalised across different process nodes (7nm, 5nm) using physics-based scaling models so that historical 7nm data could inform 5nm design decisions. (2) Multi-fidelity surrogate model: three ML models at different fidelity levels. Fast model (1ms inference): a gradient-boosted ensemble (XGBoost) trained on all 18,000 data points that predicts performance, power, and area with 88% accuracy vs. full simulation. Used for initial design space filtering — evaluating millions of configurations in minutes to identify promising regions. Medium model (100ms inference): a graph neural network that captures the processor's component interconnection topology as a graph structure. 94% accuracy vs. full simulation. Used for detailed evaluation of the top 1,000 configurations identified by the fast model. High-fidelity model (10s inference): a physics-informed neural network that incorporates semiconductor device physics (leakage current models, wire delay models, thermal constraints). 97% accuracy vs. full simulation. Used for final evaluation of the top 50 configurations before committing simulation cluster time. (3) Bayesian optimisation loop: the surrogate models are embedded in a Bayesian optimisation framework that balances exploration (sampling from uncertain regions of the design space) with exploitation (refining around known-good configurations). The acquisition function incorporates the multi-fidelity model hierarchy — using fast evaluations for exploration and high-fidelity evaluations for exploitation. Physics constraints are hard-coded: the optimiser cannot propose configurations that violate timing closure requirements, exceed the thermal design power envelope, or create physically unrealisable interconnect topologies. (4) Human-in-the-loop design review: the system presents the top 20 configurations to the design team with: Pareto front visualisation (performance vs. power vs. area — showing the trade-off surface), sensitivity analysis (which parameters most affect the result — helping designers understand why a configuration is good), and comparison to historical designs (showing where the new configuration falls relative to past successful products). Designers can add constraints ("we want to reuse the memory subsystem from our previous chip to reduce verification effort") and the system re-optimises within those constraints.

Design space coverage: the system evaluated 2.4 million configurations using the surrogate model hierarchy (vs. 800 through manual exploration — 3,000x improvement in exploration breadth). The fast model filtered 2.4M to 1,200 candidates in 40 minutes. The medium model refined to 60 candidates in 10 minutes. The high-fidelity model evaluated 60 candidates in 10 minutes. Full EDA simulation confirmed the top 5 candidates in 25 hours (vs. 3,200 hours to evaluate 800 configurations manually). Optimal design found: the system identified a configuration achieving 97.2% of theoretical optimal performance within the 5W power envelope — a 8.1% improvement over the design team's best manual exploration result. The improvement came from non-obvious parameter combinations in the memory hierarchy and interconnect topology that human designers hadn't explored. Automotive design win: the improved performance secured the autonomous driving OEM design win — $120 million in annual revenue over 5 years ($600 million total). Tape-out cycle: design exploration phase reduced from 14 weeks (manual) to 3 weeks (AI-assisted + human review) — 11 weeks saved per tape-out cycle. The design team reallocated this time to verification and validation, reducing post-silicon bug rates. Engineering productivity: the 22-person design team now uses the tool as standard workflow — each new project starts with AI exploration followed by targeted human refinement. Estimated 40% productivity improvement for the design exploration phase across all projects. Annual value: $120M in revenue from the design win (first year) + $3.2M in engineering productivity gains. Development investment: $520,000 over 20 weeks.